C.Patrick Yue
The Hong Kong University of Science and Technology, China
Prof. Yue received his BSEE from UT Austin, his Master and PhD degrees in EE from Stanford in 1994 and 1998, respectively. He has cofounded a few startups in Silicon Valley and Hong Kong, including Atheros Communications (1998), Jetcomm Technologies (2014), LiPHY Communications (2019), AIoTR Academy (2021), and High5 Semiconductor (2024) to commercialize and transfer technologies from academic to industry. He has been a professor for over two decades and has taught IC design courses and conduct research at Carnegie Mellon (2003-06), UC Santa Barbara (2006-11), Tsinghua (2015-16), HKUST (2010-now), and Stanford (1998 & 2025). He has supervised over 10 post-docs, 30 PhD and 10 MPhil student. He has published over 250 technical papers and holds over 25 patents. Together with his students and teachers, he has won a number of awards including the IEEE VLSI Circuit Symposium Test of Time Award (2024), the IEEE Circuits and Systems Society Outstanding Young Author Award (2017), and the Guanghua Engineering Science and Technology Youth Award by the Chinese Academy of Engineering (2016), and the ISSCC Best Student Paper Award (2003). Prof. Yue is a Fellow of the IEEE and Optica.
His current research interests spans over a few diverse areas including optical wireline and mmWave wireless integrated circuits, 3D computer vision models, and smart power network management system.
Speech Title: Optical PCle/CXL Interconnect for Remote GPU, Accelerator, and Memory Expansion
Abstract: Modern Gigabit Ethernet links deliver extremely high throughput—ranging from 100 Gb/s to 800 Gb/s and rapidly progressing toward terabit-class transmission—and have long integrated optical technologies through standardized optical PHYs and pluggable transceivers. As a result, Ethernet provides fiber-based server-to-server connectivity over rack-scale distances. Although Ethernet offers extremely high bandwidth and excellent scalability, it is fundamentally designed as a packet-switched network fabric rather than a device-level interconnect. Using Ethernet to attach tightly coupled resources such as GPUs, NVMe SSDs, or CXL memory would introduce unnecessary networking overhead and complexity, providing far more functionality than these device interfaces require. By contrast, PCIe is developed for direct load/store access, deterministic timing, and sub-100-ns latency. These properties make PCIe the foundational interconnect for GPUs, high-speed storage, SmartNICs, and CXL-based memory expansion. However, PCIe’s physical layer is restricted to short-reach electrical signaling over copper, which suffers from frequency-dependent attenuation, impedance discontinuities, and strong crosstalk at multi-gigahertz data rates. Optical fiber, by contrast, offers much lower loss and nearly flat bandwidth over tens of meters, making it inherently superior for long-reach high-speed transmission.
This contrast creates a fundamental architectural gap: Ethernet provides optical reach but lacks the memory semantics required for device-level attachment, whereas PCIe provides the correct semantics but lacks optical reach.Bridging this gap requires transporting native PCIe/CXL traffic over optical fiber without altering software, firmware,link-training behavior, or sideband signaling.
Motivated by this need, we demonstrate a fully optical PCIe/CXL interconnect prototype that extends GPU,accelerator, and storage devices over more than 50 meters of multimode fiber. The system preserves native PCIe/CXL semantics and operates without hardware, firmware, or software changes, enabling practical rack-scale disaggregation for future AI and cloud computing architectures.
